thermal enhancement of stacked dies using die through thermal vias

Introduction

3-dimensional (3D ) packaging technology is a method used to provide volumetric packaging solution in products . This technology uses the height , otherwise known as the third or z-dimension , for achieving higher levels of integration and performance in the products . 3D technology chiefly helps in the space-efficient integration of the multi-media functions in the products

The present trend among the consumers is to look out for products having the maximum functionality in the smallest and lightest possible package . This demand for more functions in the smallest volume , calls for higher memory

capacity , which in turn demands more complex and efficient architectures . In addition , the new product designs in digital handbook , cell phones , digital cameras , PDAs and music players , require that these features are integrated using innovative technical form factors and architectures

The 3D packaging in recent times has been associated with the delivering of the highest level of silicon integration and area efficiency at the lowest cost , smallest size and best performance . This has resulted in higher growth and brought in newer applications , for the technology This growth trend in the 3D technology can be seen since the year 1995 Prior to this , the most efficient and economic way to provide more functionality to an electronic system was to integrate all these functions onto the individual chips using the system on Chip , SOC However , this method was becoming costlier and also less efficient , as the number of functions to be integrated in a single chip further increased . In addition , some chips that could be integrated together logically were mechanically incompatible , due to the different die materials used

The present day technologies in high density packaging have reached a very advanced stage . Now a single chip system can be very efficiently split into multiple dies , so as to provide better performance at lower manufacturing costs

Over the past few years , die stacking has emerged as a powerful packaging option for satisfying challenging IC packaging requirements It works by integrating chips vertically in a single package . This increases the amount of silicon per unit area , which leads to a smaller package footprint , hence conserving system-board real estate . In addition , it enables shorter routing interconnects from chip to chip speeding the signaling between them . Heterogeneous devices can also be stacked using this technology . There is an additional benefit of the simplification of surface-mount system-board assembly , due to the lesser number of components being placed on the board

Vias - Due to the increasing number of dies in a stack , the designers are facing the challenge of meeting the temperature design specification . One method to counter this is to provide a thermal path from each individual die to a substrate using thermal vias . These thermal vias can be implemented using several methods . One of the approaches is to have a thermal die that thermally connects each die to the substrate . The heat from each die is conducted rapidly from one end of the board to another , either through the die attach or the vias Thermal vias...