Three dimensional electronics

Abstract

Packaging of electronic appliances is conventionally handled by persons other than electronics engineers , including PCB designers , substrate process specialists , circuit board assembly engineers , and specialists in thermal design . With escalating convolution of the ICs , and the need to ad infinitum reduce the size of the product , the performance of the product is not exclusive from the packaging design . The function of electronics engineer in organizations gets described relatively in frame of reference to the ever changing technologies . Contemporary electronic engineer has to work with more intricate ICs , many of which

are configurable , and circuits that operate at very high frequencies , where most designs are done using CAE , CAD , and software development tools Reliability of signals is what requires much more attention while they voyage from one IC to another , and the heat produced by ICs . The electronic engineer requires making a viable option regarding the packaging technique of the IC , blueprinting his PCB in the perspective of barriers imposed by the product standards and production facility to which he has access . Zehringer , Stuck Lang (2000

The engineer requires a good appreciation of unwrapped issues of recent day electronic gadgets

should be able to handle most of the routine packaging design issues . In this research we examine a cardinal technique of fabricating three-dimensional (3-D ) system-in-package (SiP ) employing a silicon carrier that interlock known good dice with an integrated cooling solution is made available . The centrality of this stacked module is the fabrications of silicon via a hole intersect using a wet silicon etching method . The maximization process to manipulate silicon components with solder through-hole embedded within the design tolerance has been realized . The architecture and modeling approach to maximize the package of the electrical aspects of the stacked module is conducted to realize minimal intersect parasitic . An intertwined cooling solution for 3-D stacked modules using single-phase and two-phase cooling solutions is also demonstrated for optimum performance features . Thin flip-chip is made distinctive as consigners after electrical testing . Separate known good carriers are vertically integrated to form 3-D Sip . Zehringer Stuck Lang (2000

1 .0 Introduction

Electronic packaging is the technology that deals with the development of electrical integrations and the reliable housing for the electrical circuitry . Electronic packaging of systems is one of the biggest anathema 's that faces the product design and the management aspect . Many factors need to be considered when packaging electronic appliances . This include the functionality , efficacy , cost considerations , the user friendliness and the holistic idea of dealing with the latest 3 dimensional Microsystems packaging . Thermal and electrical design configurations are also crucial , and also the modeling and simulation process is so necessary . Electronic packaging has progressively broadened to incorporate the evolution of modest technologies that are compressed and hence small and portable . The market demands has also prompted separate electronic packaging manufacturing entities thus electronic , mechanical , thermal and test engineers to cooperate and share knowledge and information across the board . The aspect of miniaturization has been the new paradigm shift that has been adopted across...