Paper Topic:

VHDL Design for Full adders

VHDL DESIGN OF FULL ADDER

Abstract

To understand digital circuit design and VHDL analysis , a simulation software tool is necessary . Xilinx 's proves to be the best choice of the available software tools . In this report , an implementation of full adder with schematic and VHDL analysis is shown . Structural and behavioural simulation output waveforms for different input signals are obtained . The occurrence and root-cause of glitches are identified Finally , the importance of Xilinx simulation tool for design and analysis of digital system design is understood

VHDL DESIGN OF FULL ADDER

p Section 1

Truth Table

The truth table for full adder is as shown in table 1

Table SEQ Table \ ARABIC 1

Cin A B S Cout

0 0 0 0 0

0 0 1 1 0

0 1 0 1 0

0 1 1 0 1

1 0 0 1 0

1 0 1 0 1

1 1 0 0 1

1 1 1 1 1 Karnaugh Maps , including details of minimization

Karnaugh Map for Sum , S is shown in table 2

Table SEQ Table \ ARABIC 2

AB

Cin 00 01 11 10

0 1

Minimisation details for Sum , S

The tabular representation of the expression of Sum , S is the relationship between the minterms . The logically adjacent 1 's are grouped together . Here every circled 1 is considered to be a group as there are no adjacent 1 's . Four groups constitute to four terms in the minimisation

Karnaugh Map for Carry , Cout is shown in table...

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